1. Field of the Invention
The present invention relates to a microprocessor device having a virtual storage system therein, more specifically to a control system for controlling a slave processor which is connected to the external part of a microprocessor to execute a portion of an instruction set.
2. Description of the related art
There exists a limit on the number of devices which can be integrated in a one-chip microprocessor composed of a large scale integrated circuit (LSI). It is, therefore, difficult for a single one-chip microprocessor to execute high level instructions such as floating point arithmetic at high speed. This is why an instruction set is classified into two kinds, each of which is executed in a master processor and a slave processor respectively.
A master processor is a processor which can operate as a central processing unit (CPU) independently of the slave processor. A slave processor is a processor which executes instructions in place of a processor under control thereof. Such a slave processor executes mainly high level instructions such as floating point arithmetic. By connecting a slave processor to a computer system in which a master processor operates as CPU, a user can expand the institution set. Intel 8086 and Intel 8087 are used as the master processor and slave processor composed of a one-chip LSI respectively.
A conventional microprocessor device comprises a master processor, a slave processor and a main storage. The master processor and the slave processor share an address/data common bus and a control bus to access the main storage. Addresses and data by which the master processor or slave processor accesses the main storage are transmitted in time division through the address/data common bus. A handshake signal line is connected between the master processor and the slave processor. The master processor, moreover, supplies an instruction decode condition signal to the slave processor so that instructions can be decoded simultaneously in both processors.
Instruction sets executed by the above microprocessor system are classified into instructions for the master processor and instructions for the slave processor.
Instructions for the master processor are the instructions by which the processor executes operation and accesses the main storage The slave processor supervises the address/data common bus and the control bus, and fetches instructions simultaneously with the master processor. The slave processor, furthermore, decodes the instructions for the master processor simultaneously with the master processor, in response to the decode condition signal from the master processor. The slave processor, however, does not execute the operation.
Instructions for the slave processor are the instructions by which the slave processor executes operation. The master processor deals with a group of instructions for the slave processor as a single instruction (hereinafter referred to as "ESC instruction"). The slave processor supervises the address/data common bus and the control bus, and fetches instructions simultaneously with the master processor. The slave processor, furthermore, decodes the instructions for the slave processor simultaneously with the master processor in response to the decode condition signal and executes the same.
Operation of the master processor and the slave processor with the instructions for slave processor depends on the presence of memory operand and on whether the memory operand is to be read or written.
(1) In case the memory operand exists:
The master processor does not execute the instructions. The slave processor executes the operation designated by the instruction for the internal register operand. (2) In case there exists memory operand
The master processor calculated the operand address and drives the bus cycle to read one word of a first address (for example 16 bits) out of the main storage. The slave processor supervises the address/data common bus and the control bus, and reads the first address of the operand and data by one word and stores them when the master processor drives the read bus cycle. The operation of the slave processor thereafter is classified into three cases depending on the reading and writing conditions.
(2-1) In the case of reading the memory operand of one word:
The slave processor executes the operation designated by the instruction for the memory operand of one word read in and the internal register operand if necessary, and stores the operation result in the internal register.
(2-2) In the case of reading the memory operand of more than two words:
The slave processor obtains the right to use the address/data bus and the control bus from the master processor in response to the handshake signal. The slave processor drives the read bus cycle by itself to read the remainder of the memory operand. Then the slave processor executes the operation designated by the instruction for the read out memory operand and the internal register operand if necessary, and stores the operation result in the internal register.
(2-3) In the case of writing to the memory operand:
The slave processor executes the operation designated by the instruction for the internal register operand. Then the slave processor obtains the right to use the address/data bus and the control bus from the master processor in response to the signal, and writes the operation result to the memory operand.
The above-mentioned conventional microprocessor system does not support the virtual storage. As a microprocessor becomes of higher performance, demand for the virtual storage which provides virtually bulk storage by using the external storage besides the main storage of the limited memory is raised, especially the virtual storage of paging method.
In the Virtue storage of the paging method, the address space which the programmer imagines (virtual address space) is divided into of several thousand bytes, and the address space is mapped to the address space of the main storage (real address space) page after page. The page which is mapped to the real address space is a portion of all the pages in the virtual space, and the remainder is undefined or exists in an external storage. In the virtual storage of the paging method, memory is protected by adding an attribute indicating whether reading out of or writing to the storage can be or cannot be executed to every page.
In a microprocessor supporting the virtual storage of the paging method, the following three checks are thus required in case of accessing the memory operand.